Graded/stepped silicide process to improve mos transistor

ABSTRACT

A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to forming conductive structures within an integrated circuit device, and in particular to forming silicides on conductive structures within an integrated circuit device. Still more particularly, the present invention relates to forming silicides of variable metal concentration as a portion of an integrated circuit device.

[0003] 2. Background of the Invention

[0004] Polysilicon layers are frequently utilized for transistor gates, interconnects, and other conductive structures within integrated circuits. To reduce the resistance of the conductive structure, doped polysilicon is often employed in those applications. While this reduces the resistance of the conductive structure, the sheet resistance remains higher than desired, e.g., between 20 and 40 Ohms/square (Ω/□). When used as a long distance conductor, the doped polysilicon interconnect may introduce a significant transmission delay.

[0005] One method to improve the sheet resistance of doped polysilicon in gate applications that does not require additional masking steps is to combine the polysilicon with a refractory metal. Refractory metal silicide films such as tungsten silicide and titanium silicide are formed on the polysilicon conductive structures (with the resulting silicide often being referred to as a “polycide”) in integrated circuits, particularly transistor gates. This process results in an improved sheet resistance, on the order of 1 to 5 Ohms/square. The use of a silicide gate reduces interconnect resistance and allows the gate to be used as a moderate long-distance interconnect. Silicide is also increasingly employed in semiconductor fabrication to reduce the contact resistance to both the gate and the source/drain conductors.

[0006] Silicide formation between a silicon and a refractory metal can be accomplished by several means. Silicides may be formed by depositing a refractory metal layer on an existing polysilicon layer, then annealing the two layers at a sufficiently high temperature to form a silicide at the interface. Alternatively, silicides may be deposited through sputter deposition from a refractory metal silicide target or by chemical vapor deposition utilizing gaseous reactants including both the refractory metal and silicon.

[0007] In conventional silicide processes, a silicide with a uniform metal concentration or stochimetric ratio (that is, the ratio x/y in Si_(x)R_(y) for a silicide formed with refractory metal R) is utilized. However, due to post silicide thermal cycles, such as poly oxidation, annealing steps, and the like, severe problems are known to occur. For example, when the Si/W ratio is low in tungsten silicide, delamination of the silicide from the underlying structure and tungsten oxidation may occur. To overcome these problems, silicon-rich silicides are commonly employed, but result in high resistivities, require large film thickness, provide poor step coverage, and degrade production throughput in both etch and deposition steps. Currently, Si/W ratios of between 2.7 and 3.3—with a resistivity of about 60 μΩ-cm—are employed in tungsten silicides as a compromise between sheet resistivity versus delamination and oxidation. As a result, transistor performance, and overall circuit performance, may be limited.

[0008] It would be desirable, therefore, to form silicides in integrated circuit devices with low sheet resistance and reduced likelihood of either delamination or metal oxidation.

SUMMARY OF THE INVENTION

[0009] A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

[0011]FIG. 1 depicts a cross-section of an integrated circuit structure including a silicide formed in accordance with a preferred embodiment of the present invention;

[0012]FIG. 2 is a more detailed view of a silicide formed in accordance with a preferred embodiment of the present invention;

[0013]FIG. 3 depicts a plot of resistivity for tungsten silicide layers as a function of the silicon/tungsten ratio; and

[0014] FIGS. 4A-4C are plots of silicon/refractory metal ratios within a silicide layer in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION

[0015] The following description details the structure, application and features of the present invention, but the process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention may be practiced in conjunction with common integrated circuit fabrication techniques, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.

[0016] With reference now to the figures, and in particular with reference to FIG. 1, a cross-section of an integrated circuit structure including a silicide formed in accordance with a preferred embodiment of the present invention is depicted. The process begins with an integrated circuit structure including a substrate 100 on which is formed an isolation oxide 102 having an opening 104 therethrough defining an active region. On a surface of the substrate 100 within the active region is a transistor gate structure including a gate oxide 106 and a polysilicon gate electrode 108. A silicide 110, described in greater detail below, is formed on the gate electrode 108. Sidewall spacers 112 are formed adjacent the gate structure, and source/drain regions 114 are formed within the substrate 100 adjacent the gate structure and partially underlying sidewalls spacers 112.

[0017] Each of the structures depicted in FIG. 1, except for silicide 110, may be formed utilizing known processing techniques. To resolve the problems described above, a silicide process with a graded or stepped silicon/refractory metal ratio is employed. Silicide 110 is formed with a variable internal composition in which the ratio of silicon to refractory metal is different at the interfaces between silicide 110 and polysilicon 108 and between silicide 110 and an overlying oxide differs from the ratio of silicon to the refractory metal within a central region.

[0018] Ideally, the silicide 110 should have both low sheet resistance and thin thickness. However, silicide delamination during subsequent thermal cycles is more prevalent among thinner silicide films, and is mainly caused by the presence of interface defects between the underlying polysilicon and the silicide (clean process), and by silicide film stress, typically resulting from lattice mismatch between the silicide and the adjoining layers. Therefore formation of a thin silicide with low sheet resistance is difficult to achieve since increasing refractory metal concentration to reduce resistivity increases stress.

[0019] Referring to FIG. 2, a more detailed view of a silicide formed in accordance with a preferred embodiment of the present invention is illustrated. Silicide 110 includes different metal concentrations, or silicon/refractory metal ratios, within different regions. A first region 110 a near the interface between silicide 110 and the polysilicon gate electrode 108 is silicon-rich, as is a second region 110 b near the opposite surface of the silicide layer 110. A central region 110 c is less silicon-rich, providing a lower resistivity for the overall structure. The silicon-rich regions near the silicide interfaces reduce the likelihood of delamination, which typically results from lattice mismatch between adjoining layers.

[0020] For example, where tungsten silicide is formed, the first and second regions 110 a-110 b, which preferably have a thickness of less than about 200 Å, may have an Si/W ratio of about 3.3. The central region 110 c, which preferably has a thickness of about 900 Å, may have an Si/W ratio of about 2.2. The silicon-rich layers near the interfaces improve lattice mismatch between the silicide 110 and the underlying polysilicon and between the silicide 110 and an overlying oxide (not shown). The central region provides a reduced resistivity for the overall structure, which is all at the same electrical potential such that the electrical properties are not significantly affected by the silicon-rich regions near the interfaces. A plot of resistivity for tungsten silicide layers as a function of the silicon/tungsten (Si/W) ratio x is depicted in FIG. 3.

[0021] Referring to FIGS. 4A through 4C, plots of silicon/refractory metal ratios within a silicide layer in accordance with a preferred embodiment of the present invention are illustrated. For chemical vapor desposition (CVD) formation of silicides, the ratio of silicon to refractory metal may be controlled by controlling the flow rates of the reactant gases. Thus, the internal composition of a silicide layer may include step changes in silicon/tungsten ratio a illustrated in FIG. 4A (i.e., formed by distinct layers), gradual changes as illustrated in FIG. 4B, or continuous changes as illustrated in FIG. 4C.

[0022] Referring back to FIG. 1, the present invention may be employed with any metal silicide, including titanium silicide, tantalum silicide, or cobalt silicide. The particular stochiometric ratios of silicon to refractory metal within regions 110 a and 110 b of silicide 110 are preferably tuned to the particular process employed and to the surface conditions of the adjoining layers. Silicide regions 110 a and 110 b thus act as “glue” layers promoting adhesion between layers, and allowing a thinner silicide 110 to be employed, consistent with smaller device feature sizes.

[0023] The present invention allows a reduction of silicide sheet resistivity to increase device performance while also reducing silicide thickness to improve topological step coverage. Thinner silicides improve productivity due to reduced thickness and increase deposition rates, and also reduces the risk of delamination. The poly depletion effect is reduced as a result of lower gate resistivity, and the risk of gate oxide degradation due to flourine penetration is also reduced. Metal oxidation on top of the silicide may be avoided due to the silicon-rich character to the upper surface region.

[0024] While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. 

What is claimed is:
 1. A method of forming a portion of an integrated circuit, comprising: forming a first silicide region over a device structure within the integrated circuit, the first silicide region having a first silicon/metal ratio; and forming a second silicide region on the first silicide region, the second silicide region having a second silicon/metal ratio greater than the first silicon/metal ratio.
 2. The method of claim 1, further comprising: forming a third silicide region between the device structure and the first silicide region, the third silicide region having a third silicon/metal ratio greater than the first silicon/metal ratio.
 3. The method of claim 2, wherein the steps of forming a first silicide region, forming a second silicide region, and forming a third silicide region further comprise: forming a silicide layer having stepped changes in silicon/metal ratio across a thickness of the silicide layer.
 4. The method of claim 2, wherein the steps of forming a first silicide region, forming a second silicide region, and forming a third silicide region further comprise: forming a silicide layer having gradual changes in silicon/metal ratio across a thickness of the silicide layer.
 5. The method of claim 2, wherein the steps of forming a first silicide region, forming a second silicide region, and forming a third silicide region further comprise: forming a silicide layer having continuous changes in silicon/metal ratio across a thickness of the silicide layer.
 6. The method of claim 2, further comprising: forming the first silicide region with a silicon/metal ratio of 2.2; and forming the second and third silicide regions with a silicon/metal ration of 3.3.
 7. A portion of an integrated circuit, comprising: a polysilicon conductive structure; a silicide on the polysilicon conductive structure; and an oxide on the silicide, wherein the silicide has higher stochiometric ratios of silicon to metal at interfaces between the silicide and the polysilicon conductive structure and between the silicide and the oxide than within an inner region of the silicide.
 8. A method of forming a portion of an integrated circuit, comprising: forming a polysilicon conductive structure; forming a silicide on the polysilicon conductive structure; and forming an oxide on the silicide, wherein the silicide has higher stochiometric ratios of silicon to metal at interfaces between the silicide and the polysilicon conductive structure and between the silicide and the oxide than within an inner region of the silicide.
 9. A portion of an integrated circuit, comprising: a first silicide region over a device structure within the integrated circuit, the first silicide region having a first silicon/metal ratio; and a second silicide region on the first silicide region, the second silicide region having a second silicon/metal ratio greater than the first silicon/metal ratio.
 10. The portion of an integrated circuit of claim 9, further comprising: a third silicide region between the device structure and the first silicide region, the third silicide region having a third silicon/metal ratio greater than the first silicon/metal ratio.
 11. The portion of an integrated circuit of claim 10, wherein the first silicide region, the second silicide region, and the third silicide region further comprise: a silicide layer having stepped changes in silicon/metal ratio across a thickness of the silicide layer.
 12. The portion of an integrated circuit of claim 10, wherein the first silicide region, the second silicide region, and the third silicide region further comprise: a silicide layer having gradual changes in silicon/metal ratio across a thickness of the silicide layer.
 13. The portion of an integrated circuit of claim 10, wherein the first silicide region, the second silicide region, and the third silicide region further comprise: a silicide layer having continuous changes in silicon/metal ratio across a thickness of the silicide layer.
 14. The portion of an integrated circuit of claim 10, further comprising: the first silicide region with a silicon/metal ratio of 2.2; and the second and third silicide regions with a silicon/metal ration of 3.3. 